[ About Us ]

The Arm Tech Symposia is a global annual event designed to share with audience the first-hand market observation, the latest Arm technology roadmap, the up-to-date diverse Arm based devices and applications. This is also a platform where partners from over 1,000 Arm Community and ecosystem gather together demonstrating their products & solutions based on Arm, exchanging market intelligence and tackling the challenges.

Through keynotes, technical presentations and booth exhibitions, chip designers, system implementation engineers, software developers, and application marketers will all be benefited. They not only can learn the latest market and technology information, but also can have face-to-face interactions with high-level executives and technology experts from Arm and industry elites from around the world.

This year, the event will be held in China, Taiwan, India, Korea, and Japan. An informative & interactive industry event which you cannot afford to miss!

[ Schedule ]

08:15 - 09:30
Pre-Function Area
09:40 - 10:15
Cornett Hall
10:15 - 10:55
Cornett Hall
10:55 - 11:15
Orchid & Senate Hall
11:50 - 13:15
Poolside - Lunch | Orchid & Senate Hall - Partner Pavilion
13:15 - 14:15
Track A - Cornett Hall | Track B - Cornett Hall | Track C - Utsav Hall
14:15 - 14:35
Orchid & Senate Hall
14:35 - 15:35
Track A - Cornett Hall | Track B - Cornett Hall | Track C - Utsav Hall
15:35 - 15:55
15:55 - 16:55
Track A - Cornett Hall | Track B - Cornett Hall | Track C - Utsav Hall
16:55 - 17:10
Orchid & Senate Hall
17:10 - 17:40
Track A - Cornett Hall | Track B - Cornett Hall | Track C - Utsav Hall
17:40 - 17:55
Orchid & Senate Hall
17:55 - 18:05
Cornett Hall
13:15 - 13:45
Track A - Cornett Hall

Discover how developers are using the Arm NN, Arm Compute Library and CMSIS-NN to develop AI applications targeting CPUs, GPUs and new processor architectures for Machine Learning (ML). After a brief overview of Arm’s ML software offerings, the talk will examine real-world use cases and how the ARM ML software libraries and APIs may be leveraged to create highly optimized ML applications for platforms ranging from Arm Cortex-M microcontrollers to Cortex-A CPUs, Arm Mali GPUs and the new Arm ML Processor. To conclude, the talk will review the roadmap for Arm NN and related low-level software libraries, while looking at some of the challenges ML presents in low-power environments.

14:15 - 14:35
Orchid & Senate Hall
14:35 - 15:05
Track A - Cornett Hall

Distributed cloud and network infrastructures, the fundamental building block in our hyper-connected world, rely upon heterogeneous computing to efficiently analyze and service vast amounts of real-time data at its source with standard virtualization and container software stacks. This talk will discuss the evolution of SmartNICs to smarter offload solutions, emerging system requirements, and detail how Arm processors, system IP, custom accelerators, and architectures, such as AMBA, PCIe, and CCIX, can be combined to customize accelerated compute solutions for hyperscale performance at the power constrained edge.

15:05 - 15:35
Track A - Cornett Hall

Discover the features and benefits of Arm’s Project Trillium's hardware processors: Machine Learning (ML) and Object Detection (OD) processors, their software support, and applicability for different markets and the options for incorporating them in differentiating SoC designs. This talk will describe our strategy and plans for the highly scalable, ground-up designed ML architecture, the markets it will target and future product iterations. It will also include a comparison with other Arm solutions, enabling you to choose the best software and hardware combination to address your specific needs.

15:35 - 15:55
15:55 - 16:25
Track A - Cornett Hall

Arm and its ecosystem partners have been working together to achieve great out-of-the-box experience for our server customers. We defined the Server Base System Architecture (SBSA) and Server Base Boot Requirements (SBBR) based on open standards. We developed the Architecture Compliance Suite (ACS) to test the servers for compliance. We designed the Arm ServerReady program to highlight the servers that comply to these standards. This session continues the public launch of the Arm ServerReady program with our partners worldwide.

16:25 - 16:55
Track A - Cornett Hall

Hyperscale data center and telco operators are evolving their platforms to enable a world of 1T connected devices, secure networks, and fast growing distributed cloud computing. A 100x increase in connected devices, driven by new IoT deployments, will require a network that can address the backhaul challenges of this increase in connected devices, while simultaneously enabling lower latency responses from networks to enable new applications such as robotics, medical, automotive V2x, and smart cities with 5G wireless technology. Those challenges require deployment of compute capability at the network edge, with low power and smart offload of networking, storage, virtualization, and ML processing – all with an abstracted software model that enables orchestration of functions to the right location in the network. In this talk, Arm will outline a technology roadmap that is specifically built for distributed cloud and 5G networks that deliver this edge computing capability. The future is cloud native, containerized, and offloaded from main data center compute, even as the main compute needs in mega data centers continue to scale. Arm is building a software ecosystem, a collection of IP, and a partnership that enables edge to cloud designs for this new infrastructure using a variety of processors, acceleration blocks, interfaces, and optimized systems. The new infrastructure will be designed with an “edge -in” heterogenous approach. The transformation in network infrastructure and cloud computing has already begun, and Arm technology is fundamental to continuing transformation of computing.

16:55 - 17:10
Orchid & Senate Hall
17:10 - 17:40
Track A - Cornett Hall

Machine Learning (ML) processing requirements vary significantly according to the network and workload; there is no ‘one-size-fits-all’ solution. Examining detailed use cases (i.e. face unlock), workloads and performance data from real networks, this talk will give examples to help you choose the right Project Trillium IP from Arm for your application – from MCUs (Arm Cortex-M) for cost- and power-constrained embedded IoT systems, through Cortex-A CPUs for moderate performance with general-purpose programmability and Arm Mali GPUs for faster performance with graphics-intensive applications to NPUs(neural processing unit), such as with the Arm ML processor, and the Arm Object Detection processor for intensive ML processing, giving the highest available performance and efficiency.

17:40 - 18:00
Orchid & Senate Hall
18:00 - 18:10
Cornett Hall
13:15 - 13:45
Track B - Cornett Hall

Today, providing more functionality at less power is driving the co-optimisation of technology, implementation and architecture. Ultra-low-power is typically associated with IoT-edge systems and local computing is increasingly moving into focus to extract information at lower sensor power. To address this multiple foundries have re-tuned larger nodes to provide lower voltage and lower leakage, and their roadmaps continue to smaller geometries. This is our call to action for substantial design optimization. We will discuss options for physical IP, its limitations, and how we must expand modelling and implementation to address ultra-low-power designs. 

13:45 - 14:15
Track B - Cornett Hall

Over the past 4-5 years, Arm has achieved significant CPU performance gains that exceed industry norms, and the recent launch of the Cortex-A76 demonstrates acceleration beyond those offered by Moore's Law with its 35% performance improvement. These gains are continuing to advance at pace, and combined with process leadership from Arm's foundry partners will deliver industry leading performance and efficiency. This talk will look at how these performance improvements were achieved and preview Arm’s Client Line of Business CPU roadmap, including future cores and their expected performance increases.

14:15 - 14:35
Orchid & Senate Hall
14:35 - 15:05
Track B - Cornett Hall

Certification, grades, functional safety and traceability are several terms that are not common for most consumer products. The rapid expansion of electronic automotive applications had made these terms much more familiar throughout the semiconductor industry. Along with these terms, we have seen the need for optimized physical IP for automotive SoC’s and a wide range of processes enabling automotive designs. We will review the advances that have been made in Artisan physical IP for automotive, the new safety package deliverables, and how the upcoming Automotive POP IP can address some of the unique and stringent requirements in the automotive space to ensure design robustness.

15:05 - 15:35
Track B - Cornett Hall

Through its continuous investment in tools and software, Arm has been accelerating system design and software development since the first Arm architecture. With compilers, debuggers and simulation systems created alongside Arm architectures and cores, Arm Development Solutions provides the tools necessary to get accurate views into your system's behavior and performance. In this session learn how Arm can help you through every step of your product development lifecycle and hear about our newest end-to-end software development tool suite.

15:35 - 15:55
16:25 - 16:55
Track B - Cornett Hall

28nm was the first node with new signoff recommendation methodology – this is where AOCV was first recommended, although many users had already adopted at earlier nodes. Then LVF quickly became popular for FinFET nodes. We will explore the reasoning for this quick transition, and cover the many different types of AOCV and LVF for signoff. The challenges for these new variation models are not only in implementation; the very definition of the model standards presents its own challenges. Join us to see the challenges we still need to solve and how this can impact your design. 

16:55 - 17:10
Orchid & Senate Hall
17:10 - 17:40
Track B - Cornett Hall

Creating the connected intelligent products of tomorrow will mean silicon vendors and product manufacturers need to design, develop and differentiate their technology today. The challenge is heightened with the need to do more processing on the edge device and providing richer user experiences - all in smaller, lower cost and lower power products. That's why application-specific designs, such as custom system-on-chips (SoCs) and FPGA-based solutions are taking off, and are becoming more accessible than ever. This talk will describe the new things that Arm and the Arm ecosystem are doing to help designers reduce cost and complexity for custom SoC and FPGA designs - describing the lower-cost and easier ways for designers to create their differentiated products and benefit from the widest choice of tools, software, and operating systems.  How do you quickly started when creating rich embedded or machine learning devices, and how do you minimise spend?  Learn how, regardless of budget and design expertise, silicon vendors and product manufacturers can reap the benefits of application-specific designs, and unleash innovation in embedded and IoT.

17:40 - 18:00
Orchid & Senate Hall
18:00 - 18:10
Cornett Hall
13:15 - 13:45
Track C - Utsav Hall

IoT devices are everywhere, and so is their data. But the data is hidden inside a variety of those devices that may be deployed in many locations on-premise or in the cloud and connected across many types of networks. Until that data is extracted and organized, its value is limited. However, when the IoT data is harnessed, unified with non-IoT data from other enterprise and third party sources, it is ready for analytics that provide insights for business acceleration. This session will discuss how Arm’s Pelion IoT Platform provides connectivity management, device management, and data management for faster time to value of IoT.

13:45 - 14:15
Track C - Utsav Hall

Modern embedded processors have a range of different security features, for example, the Arm Cortex-M processor series supports memory protection, TrustZone and physical protection. Choosing the right security technology can be critical for many applications, and this presentation will provide an in-depth explanation of each of these technologies, and the factors that need to be considered when choosing the right security approach. This talk will also cover the other key differences in Cortex-M processors, and what software changes developers need to be aware of when migrating projects to the latest Armv8-M processors. 

14:15 - 14:35
Orchid & Senate Hall
14:35 - 15:05
Track C - Utsav Hall

For IoT devices to scale, we need low-cost, low-power and high security devices across all cellular connectivity types including LPWA networks such as NB-IoT or LTE Cat 1 or Cat M. Advancements in cellular grade LTE and NB-IoT networks allow for billions of devices to be connected to operator networks, benefiting from carrier grade quality of service and security. Each of these IoT systems can be securely identified using a Subscriber Identity Module (SIM) allowing for seamless connectivity and provisioning. In this discussion, we show how connectivity technologies can benefit from stronger integration provided by ARM, with technology such as secure identity and the new iSIM form factor, now recognized as a cost and size efficient approach by OEM and Network operators. 

15:05 - 15:35
Track C - Utsav Hall

Last year at Arm TechCon, we introduced the Arm Platform Security Architecture (PSA), which is designed to provide a framework to reduce the complexity of building secure IoT devices. In 2018 so far, we have published editable IoT threat models, started an open source software project and published the first architecture documents. This presentation will first cover the basics of PSA, what we’ve achieved in the first 12 months and then new work on APIs and compliance.

15:35 - 15:55
16:25 - 16:55
Track C - Utsav Hall

Today’s IoT deployments tend to be heterogeneous and fragmented in kinds of devices and deployment topologies.  It also require a scalable, cost-effective connectivity management service.  In this talk, we will share with you knowhow on how best to make the device lifecycle managed Over-The-Air, integration choices you’ve to make to deploy in the hybrid cloud environment and best approaches to secure with commercial PKI systems.  We also discuss how to easily manage the connectivity of IoT devices, regardless of network type, and deliver ongoing connectivity management over a device’s entire lifecycle.

16:55 - 17:10
Orchid & Senate Hall
17:10 - 17:40
Track C - Utsav Hall

For the IoT and embedded market to grow and scale, device makers, OEMs and network operators need to have confidence that the IoT devices they are deploying are built with security in mind from the ground up.  Platform Security Architecture (PSA) is Arm’s response to this challenge and brings the ability for the industry to align to a common set of security design principles and good practice allowing developers and OEMs access to consistent, secure devices.  IoT security requires many complex components and a complete understanding of the IoT ecosystem. It is a significant challenge, but there is a way to make development simpler and faster.  Arm IoT solutions  build on PSA and offers out of the box compliant licensable solutions, featuring a modular approach with key components pre-integrated with security elements for multiple IoT device classes allowing SoC vendors to build secure PSA compliant IoT devices, reduce TTM and add their own market specific differentiation.

17:40 - 18:00
Orchid & Senate Hall
18:00 - 18:10
Cornett Hall

[ Sponsors ]

- Gold Sponsors -

[ Venue ]

address
Le Méridien Bangalore, Bangalore Urban, Karnataka, India, 560052